View NCS2001SN2T1_2158545.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2002 february, 2002 rev. 1 1 publication order number: and8054/d and8054/d designing rc oscillator circuits with low voltage operational amplifiers and comparators for precision sensor applications jim lepkowski senior applications engineer christopher young engineering intern, arizona state university introduction the design of rc operational amplifier oscillators requires the use of a formal design procedure. in general, the design equations for these oscillators are not available; therefore, it is necessary to derive the design equations symbolically to select the rc components and to determine the influence of each component on the frequency of oscillation. a design procedure will be shown for two state variable oscillator circuits that can be used in precision capacitive sensor applications. these two oscillators have an output frequency proportional to the product of two capacitors (c 1 *c 2 ) and the ratio of two capacitors (c 1 /c 2 ). the state variable oscillators have been built using on semiconductor's new family of sub1 volt operational amplifiers and comparators. the mc33501, mc33503, and ncs2001 operational amplifiers, and the ncs2200 comparator are the industry's first and only commercially available analog components that are specified at a voltage of 0.9 volts. these components can be powered from a single nicd, nimh or alkaline battery cell. the wide operating temperature range of 40 c to +105 c makes these devices suitable for a wide range of applications. on semiconductor's family of low voltage operational amplifiers and comparators help solve the analog limitations that have resulted from the industry's movement to low power supply voltages. the on semiconductor family of analog components provide a solution for the analog i/o interface circuits that are required for emerging low voltage dsp and microcontroller ics. there are a number of advantages that result from lowering the power supply voltage such as lower power consumption and the reduction of multiple power supplies. low voltage analog design also results in new challenges for the designer and care must be taken to transfer existing higher voltage circuits to the lower voltage levels. for example, device parameters such as the bandwidth and slew rate decrease as the voltage is reduced and are modest in comparison to traditional devices operating at voltages such as 10 v. also, there is a limited voltage swing range available at low voltages; however, this problem is minimized by the railtorail single voltage range of both the input and output signals of the on semiconductor devices. the mc33501 and mc33503 are designed with a bicmos process, while the ncs2001 and ncs2200 are implemented with a full cmos process. the main attributes of these devices are their low voltage operation and a full railtorail input and output range. the railtorail operation is provided by using a unique input stage that is formed by a folded cascade nchannel depletion mode differential amplifier. a simplified schematic of the mc33501 and mc33503 is shown in figure 1. http://onsemi.com application note
and8054/d http://onsemi.com 2 offset voltage trim output voltage saturation detector body bias clamp v cc v cc v cc v cc in out in+ figure 1. simplified schematic of the mc33501/mc33503 on semiconductor's family of low voltage operational amplifiers and comparators part number component process features package availability mc33501 mc33503 operational amplifier bicmos @ single supply operation of 1.0 v ? gain bandwidth product = 3 mhz (typ.) ? open loop voltage gain = 90 db (typ.) tsop5 available now production release 4q2000 ncs2001 operational amplifier cmos @ single supply operation of 0.9 v ? gain bandwidth product = 1.1 mhz (typ.) ? open loop voltage gain = 90 db (typ.) tsop5 available now production release 1q2001 ncs2200 comparator cmos @ single supply operation of 1.0 v ? propagation delay 1.1 s (typ.) ? complementary or open drain output configuration tsop5 product preview production release 1q2002
and8054/d http://onsemi.com 3 transducer system a wide variety of different circuits can be used to accurately measure capacitive sensors. the design choices include switched capacitor circuits, analog multivibrators, ac bridges, digital logic ics and rc operational amplifier oscillators. the requirements for a precision sensor circuit include high accuracy, reliable startup, good longterm stability, low sensitivity to stray capacitance and a minimal component count. state variable rc operational amplifier oscillators meet all of the requirements listed above; thus, they form the basis for this study. a block diagram of a capacitive sensor system is shown in figure 2. the oscillation frequency is found by counting the number of clock pulses (i.e. mhz) in a time window that is formed by the square wave oscillator output (i.e. khz) of a comparator circuit. the counter circuit can be implemented with a digital logic counter circuit or by using the time processing unit (tpu) channel of a microprocessor. if necessary, temperature correction can be accomplished by implementing a curve fitting routine with data obtained by calibrating the sensor over the operating range. an analog ic sensor can be used to monitor the sensor temperature or for very precise applications a second oscillator could be built with a platinum resistive temperature device (rtd) sensor. in addition, it is often important for the sensor system to compute the ratio of two capacitors. calculating the ratio of the capacitors reduces the transducer's sensitivity to dielectric errors from factors such as temperature. in other cases, such as in an air data quartz p pressure sensors, the desired measurement is equal to the ratio of two capacitances (c meas / c ref ). furthermore, dual sensors are typically designed to double the c meas in capacitance, while c ref may vary less than one percent. thus, the transducer's accuracy is increased if a circuit such as the ratio state variable oscillator can directly detect the c meas to c ref ratio. rc opamp oscillator comparator counter circuit temperature sensor eeprom: temperature compensation coefficients microprocessor clock clock signal oscillator signal algorithm: count the number of clock pulses in a time window set by oscillator pulses. figure 2. block diagram of capacitive sensor application c meas c ref sensor applications rc operational amplifier oscillators can be used to accurately detect both resistive and capacitive sensors; however, this paper will only analyze capacitive applications. the three basic configurations of capacitive sensors and their attributes are shown in table 1. the absolute and dual capacitive sensors will be used with the absolute and ratio oscillator circuits, respectively. differential capacitive sensors typically are not used in precision applications; therefore, they will not be analyzed in this paper.
and8054/d http://onsemi.com 4 table 1. summary of capacitive sensors sensor configuration absolute dual differential schematic representation c meas c meas c ref c 1 c 2 sensor applications ? absolute pressure ? humidity ? acceleration ? oil level ? oil quality ? differential pressure ? displacement ? proximity circuit absolute oscillator ratio oscillator typical circuit multivibrator oscillation frequency freq. c meas freq. c meas c ref freq. c 1 c 2 oscillator theory an oscillator is a positive feedback control system which does not have an external input signal, but will generate an output signal if certain conditions are met. in practice, a small input is applied to the feedback system from factors such as noise pickup or power supply transients, and this initiates the feedback process to produce a sustained oscillation. a block diagram of an oscillator is shown in figure 3. the poles of the denominator of the transfer equation t(s), or equivalently the zeroes of the characteristic equation, determine the time domain behavior of the system. if t(s) has all of its poles located within the left plane, the system is stable because the corresponding terms are all exponentially decaying. in contrast, if t(s) has one pole that lies within the right half plane, the system is unstable because the corresponding term exponentially increases in amplitude. an oscillator is on the borderline between a stable and an unstable system and is formed when a pair of poles is on the imaginary axis, as shown in figure 4. if the magnitude of the loop gain is greater than one and the phase is zero, the amplitude of oscillation will increase exponentially until a factor in the system such as the supply voltage restricts the growth. in contrast, if the magnitude of the loop gain is less than one, the amplitude of oscillation will exponentially decrease to zero. a amplifier gain feedback factor + figure 3. block diagram of an oscillator v out v in t(s) v out v in a 1 a a 1 lg a s a n(s) d(s) where a lg loop gain s characteristic equation if v in 0, then t(s) when s 0 |lg| 1 (magnitude) and lg 0 (phase). at the oscillation condition of s = 0, referred to as the barkhausen stability criterion, imaginary (j w ) imaginary (j w ) real ( w ) real ( w ) 2nd order oscillator 3rd order oscillator figure 4. pole locations for a 2nd and 3rd order oscillator
and8054/d http://onsemi.com 5 circuit descriptions absolute state variable oscillator the absolute state variable oscillator is used when the measurement is proportional to either one or two capacitors (i.e. freq. a c 1 *c 2 ). the block diagram and schematic of the absolute circuit are shown in figures 5 and 6. this circuit consists of two integrators and an inverter circuit. each integrator has a phase shift of 90 , while the inverter adds an additional 180 phase shift; thus, a total phase shift of 360 is fed into the input of the first integrator to produce the oscillation. the first integrator stage consists of amplifier a 1 , resistor r 1 and sensor capacitance c 1 . the second integrator consists of amplifier a 2 , resistor r 2 and sensor capacitance c 2 . resistorcapacitor combinations r 1 and c 1 , and r 2 and c 2 , set the gain of each integrator stage, in addition to setting the oscillation frequency. the inverter stage consists of amplifier a 3 , resistors r 3 and r 4 and capacitor c 4 . capacitor c 4 is not essential for normal operation; however, it ensures oscillator startup under extreme ambient temperature conditions. limit circuit integrator inverter integrator figure 5. absolute oscillator block diagram v 1 v 2 v 3 = 90 = 90 = 180 limit circuit figure 6. absolute oscillator schematic c1 c2 c4 r2 r3 r4 a3 a2 a1 r1 v 1 v 2 v 3 the absolute sensor capacitances c1 and c2 are used by the integration amplifiers. + + +
and8054/d http://onsemi.com 6 ratio state variable oscillator the ratio state variable oscillator [6] is used for dual capacitive sensors when the oscillation frequency is proportional to the ratio of sensor capacitances c 3 and c 4 (i.e. freq. a c 3 / c 4 ). the block diagram and schematic of the ratio circuit are shown in figures 7 and 8. this circuit consists of two integrators and a differentiator circuit. the integrators formed by amplifier a 1 and a 2 are identical to the integrators used in the absolute circuit. amplifier a 3 , resistors r 3 , r 4 and r 5 , and the sensor capacitors c 3 and c 4 form the differentiator stage which provides a 180 phase shift. the values of resistors r 3 , r 4 and r 5 are selected to set the break frequencies of the differentiator stage, so that the gain of the stage is equal to c 3 /c 4 . resistor r 5 provides a dc current path through capacitor c 3 in order to initiate oscillation at powerup. because r 5 is relatively large (m w ), it can be replaced with a three resistor ateeo network in order to use readily available resistors, as shown in figure 9. limit circuit integrator differentiator integrator figure 7. ratio oscillator block diagram v 1 v 2 v 3 q = 90 q = 90 limit circuit figure 8. ratio oscillator schematic the differentiator amplifier is formed by the dual sensor capacitances c3 and c4. c1 c2 c4 r2 r3 r4 a3 a2 a1 r1 v 1 v 2 v 3 r5 c3 ? c1 c2 c4 r2 r3 r4 a3 a2 a1 r1 v 1 v 2 v 3 r5a r5b c3 r5c r5a r5b r5c figure 9. ratio oscillator schematic with r5 tee network a tee network provides a method to replace a large resistor (i.e. m w ) with three small resistors (i.e. k w ). r 5_equivalent r 5a r 5b r 5a r 5b r 5c + + + + + + q = 180 r 5_equivalent
and8054/d http://onsemi.com 7 oscillator design procedure listed below is a procedure to design rc active oscillators: step 1: find lg and d s step 2: solve d s = 0 for s = j w o using methods i, ii or iii method i: solve remainder of n(s) s 2 o 2 = 0 method ii: solve n(j w o ) real = n(j w o ) imag = 0 method iii: routh's stability test step 3: form subcircuit design equations step 4: verify lg 1 step 1: find lg and d s the oscillation frequency is determined by finding the poles of the denominator of the transfer equation t(s), or equivalently the zeroes of the numerator n(s) of the characteristic equation d s. mason's reduction theorem, shown in appendix i, provides a method of determining the transfer equation from a signal flow diagram. mason's theorem, listed below, shows that it is not necessary to obtain the complete t(s) equation. the oscillation frequency can be determined by analyzing the numerator n(s) of the d s. d s is found by obtaining the open loop gain (lg) by breaking the feedback loop and applying a test voltage to the circuit. t(s) a 1 lg a (s) a n(s) d(s) step 2: solve d s the second step in the procedure determines the zeroes of n(s). several different control theory techniques such as the bode or nyquist stability tests can be used, or one of the three methods that are listed below. examples of the application of the three different methods listed below will be provided. method i: n(s) s 2 2 o an equation is established for the oscillation frequency w o when n(s) is divided by s 2 + w o 2 (i.e. n(s) s 2 2 o ) and the remainder is solved to be equal to zero. method i is easy to implement for second and third order systems, but with higher order systems the algebra can be tedious. method i is described in [12] and is based on factoring the characteristic equation to have a s 2 + w o 2 term. for example, when a third order system can be factored in the form (s + b )(s 2 + w o 2 ), the pole locations are at s = j w o and s = b . method i will be demonstrated by analyzing the absolute oscillator without the inverter capacitor c 4 . although the analysis of this second order system is trivial because n(s) is already in the form of s 2 + w o 2 , this method can be used for higher order circuits such as the 4 th order ratio oscillator. method ii: solve n(j o ) real = n(j o ) imaginary = 0 the oscillation equation sometimes can be determined directly from the characteristic equation by substituting s = j w o into n(s) and arranging n(j w o ) into its real and imaginary parts. this method is usually not feasible for fifth order and higher oscillators. this procedure is essentially a subset of the routh test, because the first two rows of the routh array will correspond to n(j w o ) real and n(j w o ) imaginary . if n(s) = j w o = 0, the poles of the characteristic equation will be on the imaginary axis at j w o with an oscillation frequency of w o . a summary of the oscillation equations for 2 nd and 3 rd order oscillators obtained using method ii [13] is shown in appendix ii. the application of method ii is shown for the 3 rd order absolute oscillator with the inverter capacitor c 4 . method iii: routh stability test the routh stability criterion [12] provides a method that determines the zeroes of the characteristic equation directly from the characteristic polynomial coefficients, without the necessity of factoring the equation. the routh test, shown in appendix iii, is the preferred method to use for fourth order and higher order oscillators. the routh test consists of forming a coefficient array. next, the procedure substitutes s = j w o for s, and the summation of the row is set to zero. if the row equation produces a nontrivial solution for w o , the procedure is complete and the frequency of oscillation is equal to w o . if the row equation does not yield an equation that can be solved for w o , the procedure continues with the next row in the routh array. usually, it is necessary only to complete the first two or three rows of the routh array to produce an equation that can be solved for w o . method iii will be demonstrated by analyzing the ratio oscillator. step 3: subcircuit design equations the third step in the design procedure is to form the design equations for the subcircuits formed by each operational amplifier. the oscillation equation can be simplified by selecting the r's and c's with the assumptions shown in the adesign equationo section. the amplifier gain and pole/zero locations for the absolute and ratio oscillator are also shown. step 4: verify lg 1 the final step in the procedure verifies that the loop gain is equal to or greater than one after the r's and c's component values have been chosen. this step is required to verify that the location and clamping voltage of the limit circuit will not result in a lg < 1, or that the operational amplifiers will reach their saturation voltage. the limit circuit can be located across any of the three amplifiers as long as the lg 1.
and8054/d http://onsemi.com 8 c1 c2 c4 r2 r4 a3 a2 a1 r1 v 1 v 2 v 3 r3 figure 10. absolute oscillator signal flow diagrams a 3 r 4 r 3 a 2 1 sr 2 c 2 a 2 1 sr 2 c 2 a 1 1 sr 1 c 1 a 1 1 sr 1 c 1 a 3 r 4 r 3 1 sr 4 c 4 1 v 1 v 2 v 3 v 1 v 2 v 3 without c 4 with c 4 + + + absolute oscillator design equations absolute oscillator (without c 4 ) step 1: find lg and s the loop gain is found by breaking the loop and inserting a atest'' voltage into the input. a 1 1 sr 1 c 1 a 2 1 sr 2 c 2 a 3 r 4 r 3 v test v out v 1 v 2 v 3 lg v out v test a 1 a 2 a 3 s n(s) d(s) 1 lg 1 1 sr 1 c 1 1 sr 2 c 2 r 4 r 3 1 r 4 s 2 r 1 r 2 r 3 c 1 c 2 s 2 r 4 r 1 r 2 r 3 c 1 c 2 s 2 r 1 r 2 r 3 c 1 c 2 r 4 s 2 r 1 r 2 r 3 c 1 c 2 n(s) s 2 r 1 r 2 r 3 c 1 c 2 r 4
and8054/d http://onsemi.com 9 absolute oscillator (with c 4 ) step 1: find lg and s the loop gain is found by breaking the loop and inserting a atest'' voltage into the input. a 1 1 sr 1 c 1 a 2 1 sr 2 c 2 a 3 r 4 r 3 1 sr 4 c 4 1 v test v out v 1 v 2 v 3 lg v out v test a 1 a 2 a 3 s n(s) d(s) 1 lg 1 r 4 s 3 r 1 r 2 r 3 r 4 c 1 c 2 c 4 s 2 r 1 r 2 r 3 c 1 c 2 s 3 r 1 r 2 r 3 r 4 c 1 c 2 c 4 s 2 r 1 r 2 r 3 c 1 c 2 r 4 s 3 r 1 r 2 r 3 r 4 c 1 c 2 c 4 s 2 r 1 r 2 r 3 c 1 c 2 n(s) s 3 r 1 r 2 r 3 r 4 c 1 c 2 c 4 s 2 r 1 r 2 r 3 c 1 c 2 r 4 lg 1 sr 1 c 1 1 sr 2 c 2 r 4 r 3 1 sr 4 c 4 1 r 4 s 3 r 1 r 2 r 3 r 4 c 1 c 2 c 4 s 2 r 1 r 2 r 3 c 1 c 2 a 3 z 4 z 3 r 4 || c 4 r 3 absolute oscillator (without c 4 ) step 2: solve n(s) using method i solve method i: solve the remainder of: n(s) s 2 2 o n(s) s 2 r 1 r 2 r 3 c 1 c 2 r 4 s 2 2 o r 4 2 o r 1 r 2 r 3 c 1 c 2 0 o r 4 r 1 r 2 r 3 c 1 c 2 set the remainder to equal zero and solve for o : r 1 r 2 r 3 c 1 c 2 r 1 r 2 r 3 c 1 c 2 s 2 2 o r 1 r 2 r 3 c 1 c 2 r 1 r 2 r 3 c 1 c 2 s 2 r 4 r 4 2 o r 1 r 2 r 3 c 1 c 2
and8054/d http://onsemi.com 10 absolute oscillator (with c 4 ) step 2: solve n(s) using method ii shown in appendix ii: o a 3 a 1 a 2 a 0 n(s) a 0 s 3 a 1 s 2 a 2 s a 3 s 3 r 1 r 2 r 3 r 4 c 1 c 2 c 4 s 2 r 1 r 2 r 3 c 1 c 2 r 4 a 0 r 1 r 2 r 3 r 4 c 1 c 2 c 4 a 1 r 1 r 2 r 3 c 1 c 2 a 2 0 a 3 r 4 o a 3 a 1 r 4 r 1 r 2 r 3 c 1 c 2 absolute oscillator step 3a: subcircuit oscillation design equations absolute oscillator without c 4 with c 4 n(s) r 1 r 2 r 3 c 1 c 2 s 2 r 4 r 1 r 2 r 3 r 4 c 1 c 2 c 4 s 3 r 1 r 2 r 3 c 1 c 2 s 2 r 4 o r 4 r 1 r 2 r 3 c 1 c 2 r 4 r 1 r 2 r 3 c 1 c 2 oscillation period p 2 o if r 1 = r 2 = r and r 3 = r 4 p 2 rc 1 c 2 if r 1 = r 2 = r and r 3 = r 4 p 2 rc 1 c 2
and8054/d http://onsemi.com 11 absolute oscillator step 3b: subcircuit amplifier design equations absolute oscillator without c 4 with c 4 integrator a 1 gain a 1 v 1 v 3 1 sr 1 c 1 1 2 fr 1 c 1 a 1 v 1 v 3 1 sr 1 c 1 1 2 fr 1 c 1 pole location f p1 1 2 r 1 c 1 f p1 1 2 r 1 c 1 integrator a 2 gain a 2 v 2 v 1 1 sr 2 c 2 1 2 fr 2 c 2 a 2 v 2 v 1 1 sr 2 c 2 1 2 fr 2 c 2 pole location f p2 1 2 r 2 c 2 f p2 1 2 r 2 c 2 inverter a 3 gain a 3 v 3 v 2 r 4 r 3 a 3 v 3 v 2 r 4 r 3 1 sr 4 c 4 1 pole location n a f p3 1 2 r 4 c 4 rc sensitivities* s o r 1 s o r 2 s o r 3 s o r 4 s o c 1 s o c 2 1 2 * s o r 1 s o r 2 s o r 3 s o r 4 s o c 1 s o c 2 1 2 *sensitivity is defined as: s y x y y x x d ln(y) d ln(x) absolute oscillator step 4: verify lg 1 step 4 will be demonstrating using the dual power supply limit circuit shown in figure 25. the design equations are listed below. assume: v pos_limit v neg_limit v limit |a 3 | r 4 r 3 1 v 2 v limit (i.e. |a 2 | v limit) 1.) 2.) 3.) check: is |lg| a 1 a 2 a 3 v limit 1 2 fr 1 c 1 ( v limit ) r 4 r 3 v limit 1.) using the values shown in figure 25, 1 2 (16.6 khz)(39 k ) (240 pf) (v limit )(1) v limit 2.) 1.02 v limit v limit thus the oscillation will be sustained.
and8054/d http://onsemi.com 12 c1 c2 c4 r2 r4 a3 a2 a1 r1 v 1 v 2 v 3 r3 figure 11. ratio oscillator signal flow diagrams r5 c3 v 1 v 2 v 3 + + + ratio oscillator design equations a 2 1 sr 2 c 2 a 3 r 4 (sr 5 c 3 1) (sr 3 r 5 c 3 r 3 r 5 )(sr 4 c 4 1) a 1 1 sr 1 c 1 ratio oscillator step 1: find lg and s the loop gain is found by breaking the loop and inserting a atest'' voltage into the input. a 1 1 sr 1 c 1 a 2 1 sr 2 c 2 a 3 r 4 (sr 5 c 3 1) (sr 3 r 5 c 3 r 3 r 5 )(sr 4 c 4 1) v test v out v 1 v 2 v 3 lg v out v test a 1 a 2 a 3 s n(s) d(s) 1 lg lg 1 sr 1 c 1 1 sr 2 c 2 r 4 (sr 5 c 3 1) (sr 3 r 5 c 3 r 3 r 5 )(sr 4 c 4 1) lg sr 4 r 5 c 3 r 4 s 4 r 1 r 2 r 3 r 4 r 5 c 1 c 2 c 3 c 4 s 3 [( r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 ) r 1 r 2 c 1 c 2 ] s 2 ( r 3 r 5 )( r 1 r 2 c 1 c 2 ) s 4 r 1 r 2 r 3 r 4 r 5 c 1 c 2 c 3 c 4 s 3 [( r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 ) r 1 r 2 c 1 c 2 ] s 2 ( r 3 r 5 )( r 1 r 2 c 1 c 2 ) sr 4 r 5 c 3 r 4 n(s) s 4 r 1 r 2 r 3 r 4 r 5 c 1 c 2 c 3 c 4 s 3 [( r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 ) r 1 r 2 c 1 c 2 ] s 2 ( r 3 r 5 )( r 1 r 2 c 1 c 2 ) sr 4 r 5 c 3 r 4 s 4 r 1 r 2 r 3 r 4 r 5 c 1 c 2 c 3 c 4 s 3 [( r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 ) r 1 r 2 c 1 c 2 ] s 2 ( r 3 r 5 )( r 1 r 2 c 1 c 2 ) a 3 z4 z 3 r 4 c 4 r 3 (c 3 r 5 )
and8054/d http://onsemi.com 13 ratio oscillator step 2: solve n(s) using method iii (routh's stability test) shown in appendix iii n(s) s 4 r 1 r 2 r 3 r 4 r 5 c 1 c 2 c 3 c 4 s 3 [( r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 ) r 1 r 2 c 1 c 2 ] s 2 ( r 3 r 5 )( r 1 r 2 c 1 c 2 ) sr 4 r 5 c 3 r 4 s a 0 s 4 a 1 s 3 a 2 s 2 a 3 s a 4 a 0 r 1 r 2 r 3 r 4 r 5 c 1 c 2 c 3 c 4 a 2 (r 3 r 5 )(r 1 r 2 c 1 c 2 ) a 4 r 4 a 1 [( r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 ) r 1 r 2 c 1 c 2 ] a 3 r 4 r 5 c 3 r 1 r 2 r 3 r 4 r 5 c 1 c 2 c 3 c 4 row s 4 a 0 a 2 a 4 row s 3 a 1 a 3 (r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 )r 1 r 2 c 1 c 2 (r 3 r 5) r 1 r 2 c 1 c 2 r 4 r 5 c 3 a 1 s 3 a 3 s s(a 1 s 2 a 3 ) 0 let s j o : j 3 o a 1 j o a 3 j o (a 1 2 o a 3 ) 0 2 o a 3 a 1 r 4 r 5 c 3 (r 1 r 2 c 1 c 2 )(r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 ) r 4 determine when the row s 3 equation is equal to zero. routh's stability test array ratio oscillator step 3a: subcircuit oscillation design equations n(s) s 4 r 1 r 2 r 3 r 4 r 5 c 1 c 2 c 3 c 4 s 3 [(r 3 r 5 c 3 ) (r 3 r 4 c 4 ) (r 4 r 5 c 4 )](r 1 r 2 c 1 c 2 ) s 2 (r 3 r 5 )(r 1 r 2 c 1 c 2 ) sr 4 r 5 c 3 r 4 o r 4 r 5 c 3 r 1 r 2 c 1 c 2 (r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 ) oscillation period p 2 o if r 1 r 2 r and c 1 c 2 c p 2 rc r 3 c 4 r 5 c 3 c 4 c 3 r 3 r 4 if r 5 r 3 and r 4 r 3 then p 2 rc c 4 c 3 ratio oscillator step 3b: subcircuit amplifier design equations integrator a 1 gain/pole location a 1 v 1 v 3 1 sr 1 c 1 1 2 fr 1 c 1 f p1 1 2 r 1 c 1 integrator a 2 gain/pole location a 2 v 2 v 1 1 sr 2 c 2 1 2 fr 2 c 2 f p2 1 2 r 2 c 2 differentiator a 3 gain a 3 r 4 (sr 5 c 3 1) (r 3 r 5 )(sr 3 c 3 1)(sr 4 c 4 1) dc gain r 4 r 3 r 5 gain at oscillation c 3 c 4 pole/zero locations f p1 1 2 r 4 c 4 f p2 1 2 r 3 c 3 f z1 1 2 r 5 c 3 rc sensitivities s o r 1 s o r 2 s o c 1 s o c 2 s o c 3 s o c 4 1 2
and8054/d http://onsemi.com 14 frequency (hz) gain (db) 0 oscillation range figure 12. bode plot of differentiator amplifier a 3 20x log 10 c 3 c 4 20x log 10 r 4 r 3 r 5 f p1 1 2 r 4 c 4 f p2 1 2 r 3 c 3 f z1 1 2 r 5 c 3 assumptions 1. c 3 c 4 2. c 3
c 4 3. r 3 r 4 r 5 4. r 3 r 5 and r 4
r 5 10 ratio oscillator step 4: verify lg 1 step 4 will be demonstrating using the single power supply limit circuit shown in figure 26. the design equations are listed below. assume: |a 3 | c 3 c 4 v 2 v max_limit (i.e.|a 2 | v max _ limit ) 1.) 2.) check: is |lg| a 1 a 2 a 3 v max_limit 1 2 fr 1 c 1 ( v max_limit ) c 3 c 4 v max_limit 1.) 2.) using the values shown in figure 26, 1 2 (16.5 khz)(39 k ) (240 pf) (v max_limit ) c 3 c 4 v max_limit (1.03) (v max_limit ) c 3 c 4 v max_limit 3.) oscillation will be sustained if c 3 c 4 1 1.03
and8054/d http://onsemi.com 15 component selection operation amplifiers the selection of an appropriate operational amplifier in a precision oscillator application is based on analyzing the errors caused by the amplifiers. operational amplifier errors include input offset voltage (v io ) and input bias current (i b ), open loop gain (a o ), and a finite bandwidth and slew rate (sr). the error contribution of the operational amplifier can be minimized if a low bias current, wide bandwidth amplifier is chosen. also, selecting a low oscillation frequency minimizes the dc gain and bandwidth errors. in sensor applications, only the frequency of the signal is monitored; therefore, the dc amplifier errors of v os , i b , and a finite gain will result in output signal distortion, but will not have a significant effect on the oscillation frequency. the open loop gain of almost all amplifiers will be several orders of magnitude larger than the closed loop gain of an oscillator, which typically is 1 to 2 at each amplifier. the ac amplifier errors resulting from a finite slew rate and bandwidth has a minimal effect if the oscillation frequency is relatively low (i.e. 10 khz to 20 khz). integrators + v in v out r c figure 13. ideal integrator amplifier listed below are the equations for the ideal integrator circuit formed by a single resistor and a capacitor as shown in figure 13. v out (t) 1 rc v in (t)dt v out (s) v in (s) 1 src the ideal integrator equations do not consider the effect of the amplifiers voltage offset and current bias offset errors. the effect of the offset errors is shown below [3][11]. v out (t) 1 rc v in (t)dt 1 rc v io dt 1 c i b dt v io = ideal offset error bias error where v io and i b are defined as: v io v io v io t t (temp) v io v s v s(powersupply) v io t t (time) i b i b i b t t (temp) i b v s v s(powersupply) i b t t (time) if the integrator offset and bias errors are referenced to the output, as shown below, dv out (t) dt v io rc i b c the following observations can be made: 1. use small r, large c. 2. v os 1 / rc and i b 1 / c . 3. use a low leakage current capacitor. 4. i b can be reduced if a resistor equal to the parallel combination of r and c is connected to the noninverting input of the amplifier. the error due to the operational amplifier's finite open loop gain and bandwidth, as shown below: v out (s) v in (s) 1 src 1 1 1 t os a o 1 1 sr p c = ideal (gain bandwidth error) where: r p r d r r d r r d open loop impedance t o 3 db frequency w 1 the unity gain bandwidth a o / t o if a o >> 1, the transfer equation can be simplified to: v out (s) v in (s) 1 src 1 1 1 a o t o s a o 1 a o r p cs t o a o r p c 1 src 1 1 s 1 1 a o r p cs also, there will be an error due to the amplifier slew rate and output current limitation. the slew rate error is defined as: dv out (t) dt | max 2 f p e o sr where: f p full power response e o rated output voltage the output current (i o ) of the amplifier charges the integrator feedback capacitor; thus, the integrator may have a slew rate that is less than the specified amplifier sr. the maximum rate of change of output voltage is equal to i o /c.
and8054/d http://onsemi.com 16 differentiator + v in v out c r figure 14. ideal differentiator listed below are the equations for the ideal differentiator circuit shown in figure 14. v out (t) rc dv in (t) dt v out (s) v in (s) src however, the ideal differentiator does not consider the effect of the amplifier's voltage offset and current bias errors, as shown below [3]. v out (t) rc v in (t) dt v io i b r if the output offset and bias errors are referenced to the input, as shown below, dv in (t) dt error v io rc i b c the following observations can be made: 1. use small r, large c. 2. v io 1 / rc and i b 1 / c . a practical differentiator circuit is shown in figure 15. for simplicity, this circuit will neglect the effect of resistor r 5 . there will be an error due to the operational amplifier's finite open loop gain as shown below: v out (s) v in (s) s a o 1 a o 1 r 3 c 4 s 2 s 1 r 4 c 4 1 r 3 c 3 1 r 3 r 4 c 3 c 4 if a o >> 1, the transfer equation can be simplified to: v out (s) v in (s) s 1 r 3 c 4 s 1 r 3 c 3 s 1 r 4 c 4 sr 4 c 3 sr 3 c 3 1 sr 4 c 4 1 + v in v out c3 r4 c4 r3 r5 figure 15. practical differentiator (neglect r5) the error due to the operational amplifier's finite open loop gain and bandwidth is shown graphically in figure 16. the oscillator's amplifier error and bandwidth error terms are reduced if a higher gain and increased operational amplifier is selected. the oscillation error can be minimized by selecting an oscillation frequency that is as low as practical (i.e. f oscillation @ 10 khz). the slew rate (sr) error of a differentiator is identical to the equation listed for an integrator. dv out (t) dt | max 2 f p e o sr figure 16. graphical error analysis of ideal differentiator frequency (hz) gain (db) 0 20x log c 3 c 4 20x log r 4 r 3 r 5 f p2 1 2 r 3 c 3 f z1 1 2 r 4 c 3 f p1 1 2 r 4 c 4 gain error bandwidth error a o t o open loop gain closed loop gain
and8054/d http://onsemi.com 17 voltage limit circuits automatic gain control (agc) circuits and voltage limit or bounding circuits are used in oscillators to prevent the operational amplifiers from saturating and to avoid amplifier slew rate limitations. bipolar transistors are inherently slow in coming out of saturation; therefore, a limit circuit should be used to prevent a frequency error when using amplifiers such as the bicmos mc33501 or mc33503. fet transistors do not have the slow recovery time problem coming out of saturation; however, a limit circuit should also be used with cmos operational amplifiers. the gain of the transistors in a cmos operational amplifier such as the ncs2001 will change when the transistors saturate; thus, a limit circuit is necessary to prevent an oscillation error. limit circuits will also decrease the required time for the oscillation signal to stabilize at startup. when an oscillator's poles are located exactly on the imaginary axis, the resulting waveform will be a perfect sinusoidal signal. to ensure oscillation startup the poles are adjusted to lie slightly in the right half splane causing the signal to grow exponentially until it is limited by some type of nonlinearity, such as the saturation voltage of the amplifier. agc circuits automatic gain control (agc) circuits provide a linear control of the amplifier gain to produce a constant output voltage regardless of the level of the input signal. agc circuits are usually used in applications where the level of signal distortion needs to be minimized. agc circuits are more complex than limit circuits and usually consist of an operational amplifier and/or fet that are used as a variable resistor. an example of an agc circuit is shown in figure 17. v ee agc figure 17. fet agc circuit u1 + v cc v in v out q1 r2 r1 limit circuits limit circuits are nonlinear circuits, which clamp the amplitude to a voltage level that is less than the amplifier power supply voltage. this clamping function will produce distortion in the oscillator signal. the selection of the voltage limit circuits is based on the allowable signal distortion and the simplicity of the circuit. the distortion level for most sensor oscillator circuits is relatively unimportant because only the frequency of the signal is monitored. also, limit circuits are preferable to agc circuits because they require fewer components. limit circuits typically consist of a combination of zener diodes, diodes, and transistors.
and8054/d http://onsemi.com 18 dual power supply limit circuits figure 18 shows the clamping function of the limit circuit for a dual power supply application. a simple dual supply voltage limit circuit can be created by using two backtoback zeners as shown in figure 19. there are several performance limitations with this circuit that result from the relative large junction capacitance, leakage current and temperature coefficient of a zener diode. these limitations result in a distortion of the output signal and an error in the oscillation frequency. in addition, this circuit's low voltage operation is limited to the value of the zener diode's clamping voltage (v zener ) plus the forward voltage drop (v f ) of the second zener diode. zener diodes are available in voltages of about 1.8 volts, while their forward voltage drop is typically 0.7; therefore, this circuit is not useful for voltage limiting applications below 2.5 volts. the minimum voltage range of the backtoback zener diode limit circuit can be reduced by adding two resistors to the limit circuit as shown in figure 20 [4]. the clamping value of this circuit is a function of the zener diode breakdown voltage multiplied by the ratio of the resistors. this circuit is solves the low voltage limitation of the backtoback zener limit circuit; however, this circuit is not suitable for the integrator amplifiers of the oscillator when resistor r2 is replaced by a capacitor. v in v out v neg_limit v pos_limit v in and v out figure 18. dual power supply clamping v ee figure 19. backtoback zener diode limit circuit d1 v cc v in v out r1 r2 d2 + v limit (v zener v f) v ee figure 20. backtoback zener diode limit circuit with voltage ratio resistors d1 v cc v in v out r1a r2 d2 r1b + v limit (v zener v f) * r 2 r 1b r 2
and8054/d http://onsemi.com 19 the voltage limit circuit shown in figure 21 is useful in dual power supply designs when the integrator capacitance is relatively small. a combination of two transistors and two diodes are used to make up the circuit, which limits the signal at positive and negative voltages. the diodes are used to reduce the effective capacitance of the bipolar transistors and they can be removed for low voltage applications. the operation of the limit circuits formed by the npn and/or pnp transistors can be understood by using the ebersmoll transistor model, where a transistor is modeled as a basetoemitter and a basetocollector diode. the circuit functions by setting the fixed voltage at the basetocollector junction to be less than the diode's turnon voltage; therefore, this diode is always aoff''. next, the emitter of the transistor is connected to the sine wave output of the amplifier; thus, the basetoemitter voltage (v be ) can be either greater than or less than a diode's turnon voltage. when the v be voltage is above the diode's turnon voltage, the diode is aon'' and the transistor is in the forwardactive mode of operation and the circuit clamps at a level set by the base voltage. however, when the v be voltage is below the diode turnon voltage, the junction is aoff'' and the transistor is in the cutoff mode of operation and the clamping network is effectively an open circuit. v q1_base v q2_base figure 21. dual power supply limit circuit d1 v cc v in v out d2 r q1 q2 c + v pos_limit v q1_base v q1_basetoemitter v f v q1_base (2 * 0.7) v q1_base 1.4 v v neg_limit v q2_base v q2_basetoemitter v f v q2_base (2 * 0.7) v q2_base 1.4 v v ee v q1_base 0v v q2_base 0v single power supply circuits figure 22 shows the clamping function of the limit circuit for a single power supply application [3] [4]. the limit circuit for low voltage single supply circuits can be formed by a single npn or pnp transistor. the pnp circuit shown in figure 23 is used to create the maximum voltage limit, while the npn circuit shown in figure 24 is used to form the minimum voltage limit. note that in single supply applications it is not necessary to use both the pnp and npn limit circuits. only one of the limit circuits is required to prevent the amplifiers from saturating in the state variable oscillator. v in v out t v min_limit v in and v out figure 22. single power supply clamping v max_limit figure 23. single supply maximum limit circuit v cc v in v out r q1 v q1_base c + v cc /2 v max_limit v q1_base v q1_basetoemitter v q1_base 0.7 v v ee
and8054/d http://onsemi.com 20 figure 24. single supply minimum limit circuit v cc v in v out r q1 v q1_base c + v cc /2 v min_limit v q1_base v q1_basetoemitter v q1_base 0.7 v v ee resistors and capacitors it is critical that the oscillator circuits use precision resistors and capacitors with a small temperature coef ficient (tc) and low drift rate to minimize temperature and aging errors. long term stability is typically specified for resistors and capacitors by a life test of 2000 hours at the maximum rated power and ambient temperature. in general these components have an exponential change in value for the first 500 hours of the test and are essentially stable for the remainder of the test. thus, a burnin, or temperature cycling procedure will significantly lower the drift error of the resistors and capacitors. three types of precision resistors are available: metal film, wirewound, and foil. metal film and wirewound resistors are available with a tc of 10 to 25 ppm/ c and a drift specification of approximately 0.1 to 0.5%. foil resistors are available with a tc of 0.3 ppm/ c and a drift specification of less than 20 ppm. errors with resistors are caused by both environmental and manufacturing factors. the major environmental factors causing changes in resistance are the operating power and the ambient temperature. other environmental factors such as humidity, the voltage coefficient ( d r vs. voltage), the thermal emf (due to the temperature difference between the leads and self heating), and storage will cause relatively small errors. manufacturing induced errors from factors such as soldering can cause a small change in resistance; however, this error will not effect the component's long term stability. two of the leading technologies of stable capacitors are rf/microwave multilayer porcelain and npo (cog) ceramic capacitors. the tc of porcelain capacitors is specified at +90 20 ppm/ c, while npo ceramic capacitors are available with a tc of 0 30 ppm/ c. the tc is specified over a temperature range of 55 to 125 c; however, the specification is skewed by the relatively large changes in capacitance at the extreme hot and cold temperatures. both types of capacitors have a drift specification of 200 ppm or 0.02 pf, whichever is greater, for a 2000 hour life test at 200% wvdc and a temperature of 125 c. the major error term of capacitors is due to temperature hysteresis and is specified as the retrace error. precision sensors use temperature compensation, thus a change of capacitance with temperature can be corrected; however, it is difficult to correct for hysteresis errors. other error sources are a result of the piezoelectric effect ( d c vs. voltage and pressure), the quality factor (q), and the terminal resistance. these errors are relatively small because the capacitors are designed for microwave frequencies and are specified at a wvdc well beyond the normal operating voltage of an opamp circuit. application issues remote sensing often, it is necessary to remotely locate the detection circuit from the sensor, and connect the sensor to the circuit with a shielded cable. for example, an oil level sensor for a gas turbine engine must operate at a temperature of 400 f, which is well beyond the operating capability of standard electronic components. in addition, a shielded cable is often required to limit the noise sensitivity of the measurement. the capacitance of shielded wire is typically 30 to 50 pf per foot, while the sensor capacitance is usually less than 100 pf. thus, the electronic circuit must be insensitive to the cable capacitance which will be much larger than the sensor capacitance. one approach to minimize the cable capacitance error is to use a shielded cable and the virtual ground feature of an operational amplifier when the noninverting input is grounded. this feature is inherent in the integrator and inverter/differentiator circuits used in the state variable oscillator. because an operational amplifier has a high open loop gain and input impedance, the differential voltage between the inverting and noninverting inputs is essentially zero. thus, the voltage potential at the inverting input is equal to the ground potential at the noninverting terminal. the virtual ground approach forces a constant voltage to appear across the cable capacitance; therefore, the cable capacitance does not have to be charged or discharged by the circuit and the oscillation frequency is not effected. a constant dc level at the noninverting input in the single power supply configuration is equivalent to a virtual ground because the ac level of the input terminals is equal to zero volts. the remote sensing ability of the state variable oscillator will be analyzed in detail in a future application note. reference design the reference design for the absolute oscillator is shown in figure 25. the circuit uses the bicmos mc33501 operational amplifiers operated at a power supply of 2.5v. in addition the circuit uses the dual supply limit circuit. the operating voltage of the circuit could be lowered by removing diodes d 1 and d 2 , and adjusting the base voltages of transistors q 1 (v pos_limit ) and q 2 (v neg_limit ). in the
and8054/d http://onsemi.com 21 typical application, capacitors c 1 and c 2 would be the sensor capacitances. the reference design for the ratio circuit is shown in figure 26. this circuit uses the cmos ncs2001 operational amplifiers operated at the single power supply of 0.9v. in addition the circuit uses the single supply limit circuit. in the typical application, capacitor c 3 functions as the c meas sensor while c 4 serves as the c ref sensor. the single supply vcc/2 reference voltage was obtained by using a resistor divider network. the values of the resistors r 9 and r 10 were obtained by finding the input impedances of the integrator circuits formed at amplifiers a 1 (r 1 || c 1 ) and a 2 (r 2 || c 2 ). the input bias current of the cmos amplifier is specified at only 10 pa; therefore, it is not necessary to balance the impedances at the noninverting and inverting terminals of the amplifiers. in most applications, the noninverting terminal can be connected directly to the reference voltage. figure 27 shows a voltage follower circuit that could be used to provide a more stable reference voltage with the additional benefit of a low output impedance. the ncs2200 comparator is used by the ratio oscillator design to convert the oscillator's sine wave output to a square ware digital signal. the ncs2200 is available in both a complementary and an open drain output configuration. the reference design used the open drain configuration to form a zero crossing detector. table 2 lists the calculated and measured oscillation frequency for the reference designs. the calculated frequency was obtained by measuring the r's and c's and using these values with the oscillation equations. the measured frequency of the absolute and ratio oscillators was approximately 1% different than the calculated frequency. this error between the measure and predicated oscillation frequency is probably due to the capacitance of the limit circuits, which is not included in the frequency equations. the reference designs used standard npn, pnp transistors and diodes; selecting high frequency or rf devices would minimize the oscillation error of the limiting circuit. figure 25. reference design absolute circuit c1 c2 c4 r2 r3 r4 a3 a2 a1 r1 + 39 k 240 pf 39 k + + 22 pf 10 k 10 k q1 q2 d1 d2 mps2222a mps2907a mc33501 mc33501 mc33501 240 pf 1n4001 1n4001 notes: 1. power supply voltages for amplifiers a1, a2, and a3 are v cc = 2.5 v, v ee = 2.5 v 2. v pos_limit = 1.9 v and v neg_limit = 1.9 v v q1_base = 0.5 v v q2_base = 0.5 v table 2. reference designs oscillation frequency circuit calculated oscillation frequency measured oscillation frequency absolute oscillator 16.6 khz 16.4 khz ratio oscillator 16.5 khz 16.3 khz
and8054/d http://onsemi.com 22 figure 26. reference design ratio circuit c1 c2 c4 r2 r3 r4 a3 a2 a1 r1 r6 ncs2200 + 39 k 240 pf 39 k + + 47 pf 3 meg 5 k q1 mps2907a + 1 k a4 r8 5 k v cc r7 100 k 240 pf v cc /2 ncs2001 ncs2001 ncs2001 v cc /2 v cc /2 v cc /2 c3 47 pf r5 20 meg v cc r9 39 k r10 39 k v cc /2 notes: 1. power supply voltages for amplifiers a1, a2, a3, and a4 is v cc = 0.9 v, v ee = 0 v 2. capacitors c3 and c4 are typically the sensor capacitance; however, for test purposes two 47 pf capacitors were used to verif y the circuit. 3. v max_limit = 0.8 v v q1_base = 0.1 v figure 27. low output impedance reference voltage v cc r r v cc /2 c +
and8054/d http://onsemi.com 23 appendix i: mason's reduction theorem the oscillation frequency is determined by finding the poles of the denominator of the transfer equation t(s) or equivalently the zeroes of the numerator n(s) of the characteristic equation d (s). mason's theorem (12.) states that the transfer function from input x to output y is t(s) y x i p i s i s where the terms are defined as: p i is the direct transmittance or path form input x s i is the system determinant. s i 1ifp i touches all of the loops to output y s 1 l j l k l l l m l n l n l j is the sum of all loops (i.e. loop gains) l k l l is the sum of products of pairs of nontouching loops l m l n l o is the sum of products of gains of nontouching loops taken three at a time mason's reduction theorem should be used to determine the transfer equation if the oscillator has more than one feedback loop, such as the case for the circuit shown in figure 28. obtaining t(s) also provides the additional information required to complete a bode plot of the oscillator. in contrast, step 1 of the design procedure only provides the denominator of t(s) and will not provide the numerator of the transfer equation. mason's equation can be rewritten in the form listed below: t(s) a 1 lg a (s) a n(s) d(s) the absolute and ratio oscillators only have a single feedback loop, therefore, the calculation of t(s) v 3 v 11 is relatively easy because the path p 1 (equivalent to the amplifier gain a) is defined as the voltage gain from node v 11 to v 3 and will be equal to the loop gain lg 1 . in order to calculate the transfer equation, the intermediate voltage node of v 11 is created by adding a asmallo resistor r 11 in series with resistor r 1 to the absolute and ratio circuits as shown in figures 29 and 30. adding r 11 and v 11 is not mathematically necessary; however, it greatly simplifies the algebra in the transfer equations. note, the numerator of the transfer equation depends on the definition of the input and outputs; however, the denominator (i.e. the oscillation equation) is independent of the definition of t(s). if r 1 >> r 11 , then the gain of amplifier a 1 is a function only of r 1 and c 1 . a 1 1 s ( r 1 r 11 ) c 1 1 sr 1 c 1 listed below are the calculation of t(s) for the absolute oscillator with and without capacitor c 4 and the ratio oscillator. c1 c2 r2 r4 a3 a2 a1 r1 r3 figure 28. mason's theorem provides a method to determine the transfer equation t(s) of an oscillator when there are multiple feedback loops, as with the modified absolute circuit r5 + + + v1 v2 v3
and8054/d http://onsemi.com 24 c1 c2 c4 r2 r4 a3 a2 a1 r1 v 1 v 2 v 3 figure 29. schematic of the absolute oscillator with rll that is used to obtain t(s), using mason's reduction theorem r3 + r11 v11 + + absolute oscillator (without c 4 ) assume r 1 >> r 11 , then r 1 + r 11 r 1 s 1 lg 1 1 1 sr 1 c 1 1 sr 2 c 2 r 4 r 3 1 r 4 s 2 r 1 r 2 r 3 c 1 c 2 s 2 r 1 r 2 r 3 c 1 c 2 r 4 s 2 r 1 r 2 r 3 c 1 c 2 t(s) v 3 v 11 p 1 s r 4 s 2 r 1 r 2 r 3 c 1 c 2 s 2 r 1 r 2 r 3 c 1 c 2 r 4 s 2 r 1 r 2 r 3 c 1 c 2 r 4 s 2 r 1 r 2 r 3 c 1 c 2 r 4 p 1 lg 1 a 1 a 2 a 3 1 sr 1 c 1 1 sr 2 c 2 r 4 r 3 absolute oscillator (with c 4 ) assume r 1 >> r 11 , then r 1 + r 11 r 1 p 1 lg a 1 a 2 a 3 p 1 lg 1 sr 1 c 1 1 sr 2 c 2 r 4 r 3 1 sr 4 c 4 1 r 4 s 3 r 1 r 2 r 3 r 4 c 1 c 2 c 4 s 2 r 1 r 2 r 3 c 1 c 2 s 1 lg 1 r 4 s 3 r 1 r 2 r 3 r 4 c 1 c 2 c 4 s 2 r 1 r 2 r 3 c 1 c 2 s 3 r 1 r 2 r 3 r 4 c 1 c 2 c 4 s 2 r 1 r 2 r 3 c 1 c 2 r 4 s 3 r 1 r 2 r 3 r 4 c 1 c 2 c 4 s 2 r 1 r 2 r 3 c 1 c 2 t(s) p 1 s r 4 s 3 r 1 r 2 r 3 r 4 c 1 c 2 c 4 s 2 r 1 r 2 r 3 c 1 c 2 s 3 r 1 r 2 r 3 r 4 c 1 c 2 c 4 s 2 r 1 r 2 r 3 c 1 c 2 r 4 s 3 r 1 r 2 r 3 r 4 c 1 c 2 c 4 s 2 r 1 r 2 r 3 c 1 c 2 r 4 s 3 r 1 r 2 r 3 r 4 c 1 c 2 c 4 s 2 r 1 r 2 r 3 c 1 c 2 r 4
and8054/d http://onsemi.com 25 c1 c2 c4 r2 r4 a3 a2 a1 r1 v 1 v 2 v 3 r3 figure 30. schematic of the ratio oscillator with rll that is used to obtain t(s), using mason's reduction theorem. r5 c3 + ratio oscillator r11 v11 + + ratio circuit assume r 1 >> r 11 , then r 1 + r 11 r 1 p 1 lg a 1 a 2 a 3 1 sr 1 c 1 1 sr 2 c 2 r 4 (sr 5 c 3 1) (sr 3 r 5 c 3 r 3 r 5 )(sr 4 c 4 1) p 1 lg 1 (sr 4 r 5 c 3 r 4 ) s 4 r 1 r 2 r 3 r 4 r 5 c 1 c 2 c 3 c 4 s 3 r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 r 1 r 2 c 1 c 2 s 2 r 3 r 5 r 1 r 2 c 1 c 2 s 1 lg 1 s 4 r 1 r 2 r 3 r 4 r 5 c 1 c 2 c 3 c 4 s 3 r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 r 1 r 2 c 1 c 2 s 2 r 3 r 5 r 1 r 2 c 1 c 2 sr 4 r 5 c 3 r 4 s 4 r 1 r 2 r 3 r 4 r 5 c 1 c 2 c 3 c 4 s 3 r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 r 1 r 2 c 1 c 2 s 2 r 3 r 5 r 1 r 2 c 1 c 2 t(s) v 3 v 11 p 1 s (sr 4 r 5 c 3 r 4 ) s 4 r 1 r 2 r 3 r 4 r 5 c 1 c 2 c 3 c 4 s 3 r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 r 1 r 2 c 1 c 2 s 2 r 3 r 5 r 1 r 2 c 1 c 2 s 4 r 1 r 2 r 3 r 4 r 5 c 1 c 2 c 3 c 4 s 3 r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 r 1 r 2 c 1 c 2 s 2 r 3 r 5 r 1 r 2 c 1 c 2 sr 4 r 5 c 3 r 4 s 4 r 1 r 2 r 3 r 4 r 5 c 1 c 2 c 3 c 4 s 3 r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 r 1 r 2 c 1 c 2 s 2 r 3 r 5 r 1 r 2 c 1 c 2 (sr 4 r 5 c 3 r 4 ) s 4 r 1 r 2 r 3 r 4 r 5 c 1 c 2 c 3 c 4 s 3 (r 3 r 5 c 3 r 3 r 4 c 4 r 4 r 5 c 4 )r 1 r 2 c 1 c 2 s 2 r 3 r 5 r 1 r 2 c 1 c 2 sr 4 r 5 c 3 r 4
and8054/d http://onsemi.com 26 appendix ii: method ii: solve n(j w o ) real = n(j w o ) imaginary = 0 the oscillation equation sometimes can be determined directly from the characteristic equation by substituting s = j w o into d s and arranging the n(j w o ) into its real and imaginary parts. however, this method is usually not feasible for circuits which are fifth order and higher oscillators. this procedure is essentially a subset of the routh test, because the first two rows of the routh array will correspond to n(j w o ) real and n(j w o ) imaginary . if the characteristic equation n(s) = j w o = 0, the poles of the characteristic equation will be on the imaginary axis at j w o with an oscillation frequency of w o . the method ii procedure is shown below for second and third order oscillators [13]. secondorder circuits n 2(s) a 0 s 2 a 1 s a 2 a 0 s 2 a 1 a 0 s a 2 a 0 let s = j w o be the frequency at which n 2 (s) = 0. the condition for oscillation is meet when the a 1 term is set to zero, and the sterm is removed. the frequency of oscillation is found from: o a 2 a 0 third order circuits n 3 (s) a 0 s 3 a 1 s 2 a 2 s a 3 let s = j w o be the frequency at which n 3 (s) = 0, and arrange the equation into its real and imaginary parts: n 3 (j o ) (a 1 2 o a 3 ) j o (a 0 2 o a 2 ) 0 thus, the real and imaginary parts equal zero when: a 1 2 o a 3 0 and a 0 2 o a 2 0 solving the above equations for o 2 gives: 2 o a 3 a 1 a 2 a 0 summary of method ii equations oscillator order n(s) oscillation condition o 2nd n 2 (s) a 0 s 2 a 1 s a 2 a 1 0 o a 2 a 0 3rd n 3 (s) a 0 s 3 a 1 s 2 a 2 s a 3 a 1 a 2 a 0 a 3 o a 3 a 1 a 2 a 0
and8054/d http://onsemi.com 27 appendix iii: routh's stability test routh's stability test [12] can be used to test the characteristic equation to determine whether any of roots lie on the imaginary axis. routh's test consists of forming a coefficient array. next, the procedure substitutes s = j w o for s, and the summation of the row is set to zero. if the row equation produces a nontrivial solution for w o , the procedure is complete and the frequency of oscillation is equal to w o . if the row equation does not yield an equation that can be solved for w o , the procedure continues with the next row in the routh array. this technique arranges the numerator of the characteristic equation (i.e. denominator of the transfer equation) into the array listed below. t(s) a 1 lg a (s) a n( s) d( s) n( s) a 0 s n a 1 s n 1 a 2 s n 2 a 3 s n 3 ... a n 1 s a n s n a 0 a 2 a 4 a n s n1 a 1 a 3 a 5 a n1 s n2 b 1 b 2 b 3 b n2 s n3 c 1 c 2 c 3 c n3 .... .. . . .. . s 0 f 1 where the coefficients b 1 , b 2 , b 3 , etc., are evaluated as follows: b 1 a 1 a 2 a 0 a 3 a 1 b 2 a 1 a 4 a 0 a 5 a 1 b 3 a 1 a 6 a 0 a 7 a 1 the evaluation of the b's is continued until the remaining terms are equal to zero. the same pattern of cross multiplying the coefficients of the two previous rows is followed in evaluating the c's, d's, etc... c 1 b 1 a 3 b 2 a 1 b 1 c 2 b 1 a 5 b 3 a 1 b 1 this process is continued until the n th row has been completed. the routh stability criterion states: 1. a necessary and sufficient condition for stability is that the first column of the array does not contain sign changes. 2. the number of sign changes in the entries of the first column of the array is equal to the number of roots in the right half splane. 3. if the first element in a row is zero, it is replaced by e , and the sign changes when e 0 are counted after completing the array. 4. the poles are located in the right half plane or on the imaginary axis if all the elements in a row are zero.
and8054/d http://onsemi.com 28 bibliography 1. baxter, l., acapacitive sensors offer numerous advantageso, electronic design, january 26, 1998. 2. celma, c., martinez p., carlosens, a., aapproach to the synthesis of canonic rcactive oscillators using cciio, iee proc. circuits, devices and systems, vol. 141, no. 6, december 1994, pp. 493497. 3. clayton, g. and winder, steve, operational amplifiers (4th edition), newness, boston, 2000. 4. graeme, jerald, amplifier applications of op amps , mcgraw hill, n.y., 1999 5. griffith, r., vyne, r., dotson, r., and petty, t, aa 1v bicmos railtorail amplifier with nchannel depletion mode input state,o ieee journal of solidstate circuits, vol. 32, no. 12, dec. 1997, pp. 2012 2022. 6. lepkowski, j. and et. al, acapacitive pressure transducer systemo, u.s. patent no. 4,987,782, issued jan. 29, 1991. 7. lindquist, c., active network design with signal filtering applications , steward and sons, long beach, 1977. 8. martinez, p., aldea c. and celma, s., aapproach to the realization of state variable based oscillatorso, ieee international conference on electronics circuits and systems, vol. 3, 1998, p. 139142. 9. pease, robert, abounding, clamping techniques improve circuit performance,o edn, nov. 10, 1983. 10. sidorowicz, r. aan abundance of sinusoidal rcoscillatorso, proc. iee, vol. 119, no. 3, march 1972, pp. 283293. 11. stata, ray, aan357: operational integrators,o analog devices, norwood, ma, 1967. 12. truxal, j. introductory system engineering , mcgrawhill, n.y., 1972. 13. van valkenburg, m., analog filter design , saunders college publishing, fort worth, 1992. on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. and8054/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

▲Up To Search▲

Price & Availability of NCS2001SN2T1

	To Download NCS2001SN2T1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .